An exciting day here – after several months of delays (firstly due to me procrastinating followed by production delays due to Coronavirus) the PCBs for my retro m68k computer have arrived!
I eventually decided to have these made by JLCPCB in China, and I have to say I’m very impressed with the quality and finish. On unpacking I immediately noticed a couple of things I didn’t spot before sending the gerbers off, but those are my mistakes – the fab is actually pretty much perfect. Drill is spot on and the silkscreen is lined up perfectly.
Obviously how satisfied I am may change once I get the components soldered on, but I’m pretty confident that the board will be absolutely fine. I’ll update here once I’ve done that.
I’m writing regular logs on hackaday.io about the m68k-based retro computer I mentioned I was building a while back, but I thought I’d post a quick update here too. If you’re interested in the project, be sure to follow it on hackaday as that’s where the regular updates are going.
The main progress so far has been:
Get the CPU free-running
Decide on a memory layout, and design an address decoder to support that layout
Build the address decoder
Decide how I want to lay the buses out on the board for easier interconnection
Actually wire up the buses accordingly
I actually designed the address decoder a while ago, but gathering the parts and then wiring it up has taken some time – I finished it yesterday. Since then, I’ve been breaking out the CPU signals onto control, data and address buses, which I’m doing on an otherwise-bare breadboard in the middle of the main boards.
Right now, the rosco_m68k looks like this:
It’s still free-running at the moment (I’ve not wired the memory to the bus yet as you can see) but all the control pins I care about (basically everything except the legacy 6800 peripheral pins and the function code) are now on the control bus. The jumpers you can see there are configuring those control pins for free-run mode and will be replaced by connections to the RAM and ROM.
I did come across a couple of design errors while building the address decoder, some of which I fixed and others I’ve decided I can live with for now (e.g. an issue with the expansion select line I only discovered once I’d completely built the decoder and hooked up the LEDs at bottom left).
Anyway, that’s where it’s at right now. I expect that after another day’s wiring, it’ll be ready to run real code, and I can’t wait.
Somewhere around the time I got bored with Advent of Code 2018 (well, the challenges grew to become total time-sinks), I decided my project for the new year was going to be a homebrew retro computer.
I decided that, rather than something 8-bit based on the Z80 or 6502, I wanted to go up a generation and build something 16-bit.
Apart from gaming and a bit of BASIC programming on 8-bit machines like the Spectrum and C64, my first “real” computing was done on the Amiga, a machine which still has a special place in my heart today. For that reason, I decided I wanted to build something based on the Motorola 68000 series processor.
I chose the 68010 which (as far as I’m aware) was never used in the Amiga line, but which is slightly more capable than the 68000 (e.g. interrupt vectors can be moved around and it can support virtual memory when used with a 68451 MMU, though I’m not likely to do the latter in this build). Mine is rated for 10MHz, but I’m only running it at 4MHz at the moment).
The key differences between this and an 8-bit Z80 or 6502 build are:
Dynamic registers, so the clock cannot be stopped or single-stepped (this can be emulated by manipulating /DTACK though).
Asynchronous data bus and DMA support, with /BGR, /BGA, /BERR and /DTACK to take care of.
16-bit data bus, so more wires needed.
24-bit (with some caveats) address bus, so lots more wires needed, but 16MB of address space available!
Internally, the m68k family is 32-bit.
/UDS and /LDS lines for selecting upper and lower data bytes, so a more complicated address decoder and ROM/RAM in pairs.
No separate IO space, further complicating the address decoder.
More complicated requirements around /RESET and /HALT handling, especially at power-on.
I started gathering parts in January, and so far have the crystal clock circuit, the reset/halt circuit, and have gotten the CPU freerunning with /DTACK grounded and the various other bus management lines tied high or low as appropriate.
The address decoder is designed, and I already have the RAM and ROM chips ready to go. I’ve also built an EEPROM programmer because I’m too impatient/cheap to order one and wait for it to arrive.
All this means that, pretty soon, I should be able to get it running some actual code!
Fun times are ahead! If you’re interested, you can follow the project over on Hackaday.